| Please be advised that the National Institute of Standards and Technology (NIST) has released a Notice of Funding Opportunity (NOFO) for its Small Business Innovation Research (SBIR) Program for CHIPS For America – CHIPS Metrology. The NOFO number is 2024-SBIR-CHIPS-01. This NOFO closes on Friday, June 14, 2024 Eastern Time. More information about this NOFO can be found at the following websites: https://grants.gov/search-results-detail/353574 https://www.nist.gov/sbir This NOFO includes both grand challenges (open topics) as well and more focused needs (closed topics). Many of these topics align with DOE funded areas such as microelectronics, electron microscopy, and x-ray sources. Open Topics: Recognizing that metrology is critical to enabling future microelectronics innovation, NIST has worked with stakeholders to identify the critical challenges requiring R&D. Information gained by NIST through a series of workshops, a request for information, and discussions with major companies has informed a proposed strategic path forward focused on seven Grand Challenges, outlined in the Strategic Opportunities for U.S. Semiconductor Manufacturing publication. For the Open Topic SBIR Section, the CHIPS Metrology SBIR program seeks applicants to propose innovation that relates to an outlined path forward elements identified in the Metrology Grand Challenges. Grand Challenge 1: Metrology for Materials Purity, Properties, and Provenance The challenge: Meet increasingly stringent requirements for semiconductor materials purity, physical properties, and provenance across a diverse supply chain through development of new measurements and standards. Grand Challenge 2: Advanced Metrology for Future Microelectronics Manufacturing The challenge: Ensure that critical metrology advances are made to keep pace with cutting-edge and future microelectronics and semiconductor manufacturing, while maintaining a competitive U.S. advantage. Grand Challenge 3: Enabling Metrology for Integrating Components in Advanced Packaging The challenge: Provide enabling metrology that spans multiple length scales and physical properties and supports acceleration of advanced packaging concepts for future-generation microelectronics. Grand Challenge 4: Modeling and Simulating Semiconductor Materials, Designs, and Components The challenge: Improve the tools needed to effectively model and simulate future semiconductor materials, processes, devices, circuits, and microelectronic system designs. Grand Challenge 5: Modeling and Simulating Semiconductor Manufacturing Processes The challenge: Seamlessly model and simulate the entire semiconductor value chain, from materials inputs to chip fabrication, system assembly, and end products. Grand Challenge 6: Standardizing New Materials, Processes and Equipment for Microelectronics The challenge: Create the standards and validation methods necessary to accelerate the development and manufacturing of future information and communication technologies. Grand Challenge 7: Metrology to Enhance Security and Provenance of Microelectronic-based Components and Product The challenge: Create the metrology advances needed to enhance the security and provenance of microelectronic components and products across supply chains and increase trust and assurance. Closed Topics: The CHIPS Metrology Program has also funded research & development projects teams, comprised of NIST researchers with collaborative partners from industry, academia, and other government/nonprofit research centers, to address the highest priority metrology challenges aligned with the Seven Metrology Grand Challenges. Several of these teams are specifically seeking SBIR applicants with the following innovative technology with whom they'd work collaboratively related to the following topics. Please note, applicants that have related, successfully completed Phase I awards from NIST or another federal agency are eligible to submit for a Phase II application to the Closed Topics. All other applicants should submit for a Fast Track Phase 1 and Phase 2 award for these Closed Topics. - Closed Topic Title: Near-Real Time RF Propagation Measurement System
- Closed Topic Title: Compact, fieldable cryogenics for deployment of superconducting-nanowire single-photon detectors in a circuit-evaluation microscope
- Closed Topic Title: Microscope for time-resolved emission microscopy with superconducting-nanowire single-photon detectors
- Closed Topic Title: Device-Scale AFM-Thermoreflectance Hybrid Metrology
- Closed Topic Title: Super-resolution beam scanning, wide bandwidth, optical photothermal infrared (O-PTIR) microscope.
- Closed Topic Title: High brightness compact X-ray or EUV sources for semiconductor metrology
- Closed Topic Title: Nanoscale dimensional metrology reference standards to support semiconductor metrology
- Closed Topic Title: Advanced Electron Backscatter Diffraction (EBSD) detector offering high pixel density, high-speed and low noise operation, and low kV detection enabled by directly detecting electrons using an application specific integrated circuit (ASIC) detector.
- Closed Topic Title: TEM High Voltage Biasing Holder
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